Senior Digital Verification Architect

Infineon Technologies AG in Villach, Austria, seeks a Senior Staff Engineer in Digital Verification to define verification plans and lead a team of verification engineers. You will develop verification environments in SystemVerilog/UVM, write tests for RTL and gate-level, and collaborate closely with architects and designers.

The role requires a university degree in electronics-related fields, 6+ years in digital verification, and strong SystemVerilog/UVM expertise.