Senior RTL Design Architect (Verilog/SystemVerilog)

Vivid Resourcing Ltd seeks a Senior Digital Design Engineer to lead digital hardware development from architecture through RTL implementation. You will translate system requirements into robust digital designs, owning blocks and collaborating with verification and systems teams.

The role involves hands-on RTL coding in Verilog/SystemVerilog and mentoring junior engineers, with a focus on delivering high-quality digital solutions across ASIC/FPGA/SoC contexts.